This invention relates generally to a semiconductor structure manufacturing method and more particularly to a complementary metal electrode semiconductor (CMES) device.
As is known in the art relatively low power, high speed, digital logic circuits have been designed using complementary MOSFET (metal oxide semiconductor field effect transistor) technology. The complementary MOSFET (also referred to as CMOS) is formed by interconnecting n-channel and p-channel field effect transistors on a single crystal substrate which results in a CMOS device with very low static power dissipation.
In general, when complementary MOSFETs are used to perform logic operations, power is only dissipated when operating in the "active" mode. The "active" mode occurs when the logic inputs are being continually exercised at a frequency (f) producing a proper logic output at the same frequency. The active power dissipation is proportional to this frequency (f), the square of the logic voltage, V2, and the active capacitance, C, which is charged and discharged. Thus, P .varies. CV2f, and the total "active" power dissipation is proportional to the number of these logic functions being exercised at a particular operating frequency.
However, with the advent of very large scale integrated circuits (VLSI) using 1.0 micron process technology and the next generation expectations of sub-micron process technology, the resulting high density integration of high speed circuits provides semiconductor devices having undesirable active power dissipations and establishes the need for a much lower power, high speed semiconductor technology. As can be seen in the power relation, the power dissipation is directly proportional to the square of the logic voltage. If this can be reduced by a factor of 5 to 10, then the resulting active power dissipation would be reduced by a factor of 25 to 100. A complementary MESFET device can provide this power reduction if both the n-MESFET and the p-MESFET are both operating as enhancement mode devices.
An n-channel MESFET is formed by creating a Schottky barrier on n-type silicon between two heavily doped regions (n+) called the source and drain. A p-channel MESFET is formed by creating a Schottky barrier on p-type silicon between two heavily doped regions (p+), similarly called the source and drain. For the most efficient operation of such Schottky barriers in controlling the flow of charge between respective sources and drains, it is required that they have the highest "barrier" energies possible. This is not achievable using conventional techniques for forming n-channel and p-channel MESFETS on the same silicon wafer.